1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device and, more specifically, to a semiconductor device having a through connection portion for electrically connecting wirings on the front and rear surfaces of a semiconductor substrate and a method manufacturing thereof.
2. Description of the Related Art
It is proposed, in a memory device using a semiconductor integrated circuit, to layer memory chips (semiconductor chips) at multiple tiers to enhance the memory capacity. The semiconductor chip is formed with a through hole penetrating through its front and rear surfaces, a conductor layer is formed in the through hole, and a metal bump conducted to the conductor layer is formed on the rear surface of the chip. The metal bump of the semiconductor chip at the upper tier is bonded to a metal pad formed on the front surface of the semiconductor chip at the lower tier, thus electrically connecting the integrated circuit of the memory chip at the upper tier to the integrated circuit of the memory chip at the lower tier.
As a semiconductor device having such a through connection portion, a device has conventionally been proposed which has a structure in which a through hole is formed by etching from the rear surface of a semiconductor substrate so that wirings on the front surface and rear surface of the semiconductor substrate are electrically connected via a conduction portion formed in the through hole (see, for example, U.S. Pat. No. 5,229,647 and Japanese Patent No. 3,186,941, and JP-A 2001-68618 (KOKAI)).
Hereinafter, a conventional semiconductor device is described. In a conventional semiconductor device 100 shown in FIG. 8, a semiconductor substrate 101 made of silicon has a through hole 102 penetrating through its front and rear surfaces, and an insulating film 103 is formed from on an inner wall surface of the through hole 102 to on the rear surface of the semiconductor substrate 101. In addition, a through wiring layer 104 is formed in the through hole 102. The through wiring layer 104 electrically connects a wiring layer (a front surface side wiring layer) 105 formed on the front surface side of the semiconductor substrate 101 to an external terminal (a solder ball) 106 formed on the rear surface side. On the front surface side of the semiconductor substrate 101, an insulating layer (a front surface side insulating layer) 107 is formed, on which the front surface side wiring layer 105 is formed, and a front surface side protective film 108 is further formed on the front surface side wiring layer 105. On the front surface side of the semiconductor substrate 101, a semiconductor device such as an image sensor or the like is formed of an integrated circuit. On the rear surface side of the semiconductor substrate 101, the external terminal 106 connected to the through wiring layer 104 and a rear surface side protective film 109 are formed. The external terminal 106 is formed to protrude to the outside.
In this semiconductor device 100, the through hole 102, an opening 107a of the front surface side insulating layer 107, and an opening 103a of the insulating film 103 have the same shape and substantially the same diameter and are formed as described below. Specifically, the through hole 102 is formed by etching the semiconductor substrate 101 using a predetermined mask pattern (not shown) from its rear surface side until the front surface side insulating layer 107 is exposed. Subsequently, using the formed through hole 102 as a mask, the front surface side insulating layer 107 is etched by the etching method with a greater selection ratio than that of the semiconductor substrate 101, whereby the opening 107a of the front surface side insulating layer 107 is formed. Further, the rear surface side insulating film 103 is formed on the inner wall surface of the through hole 102 and on the rear surface of the semiconductor substrate 101 such that the insulating film 103 has a larger film thickness on the rear surface side of the semiconductor substrate 101 than on the bottom surface and the inner wall surface of the through hole 102, and the rear surface side insulating film 103 is etched back using the anisotropic etching. Thus, the insulating film 103 on the bottom surface of the through hole 102 is removed to expose the wiring layer 105.
However, in the semiconductor device 100 manufactured in such a method, the exposed wiring layer 105 on the front surface side has been thinned during opening the front surface side insulating layer 107 and the rear surface side insulating film 103, resulting in decreased mechanical reliability. Further, another problem is that more thinning results in a loss of a portion of the wiring layer 105 to cause a poor connection with the through wiring layer 104, leading to a reduced yield.